CCD gain control

ABSTRACT

The present circuit is applicable to buried channel charge coupled devices (CCD&#39;s) of the type having an input circuit which employs a &#34;skimming&#34; technique for producing a charge representing an input signal. A given amount of charge initially is present in an input potential well of the CCD and an amount of charge representing an input signal is skimmed therefrom for propagation down the CCD, leaving behind a residual charge which continuously remains in the input potential well. The gain of the input circuit of the CCD is controlled by controlling the amount of this residual charge either in open loop fashion or by means of feedback. A comb filter suitable for separating the luminance and chrominance components of a television signal which includes this circuit is also described.

This is a continuation of application Ser. No. 821,100 filed Aug. 2,1977, now abandoned.

The present invention relates to gain control circuits for chargecoupled devices (CCD's) and to systems including such circuits.

IN THE DRAWING:

FIG. 1 is a section through a CCD embodying the invention;

FIG. 2 is a plan view of the CCD of FIG. 1;

FIG. 3 is a drawing of waveforms employed for operating the CCD of FIGS.1 and 2;

FIG. 4 is a drawing of substrate potential profiles to help explain theoperation of the CCD of FIGS. 1 and 2;

FIG. 5 is a drawing of the electron energy bands of a CCD embodying theinvention;

FIG. 6 is a family of graphs to help explain the operation of the CCD ofFIGS. 1 and 2;

FIG. 7 is a schematic showing of a system embodying the invention; and

FIG. 8 is a schematic showing of a system including a feedbackcontrolled embodiment of the invention.

Copending U.S. application Ser. No. 758,184 for "Linear CCD InputCircuit," filed Jan. 10, 1977 by J. E. Carnes, P. A. Levine (the presentinventor), and D. J. Sauer and assigned to the same assignee as thepresent application, discusses a particular kind of input circuit for aburied channel CCD. This circuit colloquially is now referred to as a"fan and skim" input circuit. It is especially useful in CCD delay linesemployed to delay analog signals such as the video signals of televisionas it permits linear signal translation.

The CCD signal register shown in section in FIG. 1 and in plan view inFIG. 2, except for the gain control circuit, is similar to the CCDregister described in the above-identified application. However, thepresent system, by way of example, utilizes self-aligned barrierimplants such as 85 and 87 under the second layer of gate electrodes(rather than DC offsets between electrode pairs) to obtain asymmetricalpotential wells in the substrate for permitting unidirectional chargepropagation with two phase clocking. Typical processing parameters for aburied N-channel CCD with this structure are: (1) Substrate: P-type30-50 Ω-cm resistivity; (2) N-type buried layers implant: Phosphorous,Dose=1.3×10¹² /cm², Energy=150 keV, junction depth X_(j=) 0.75 micron;(3) P-type barrier implant: Boron, Dose=4×10¹¹ /cm², Energy=100 keV.

As in the register of the copending application, the present CCDincludes electrodes G₁, G₂ and G₃ and these are followed by multiplephase electrodes. The electrodes G₁, G₂ and G₃ are operated in such away that a residual charge level Q_(F) (FIG. 4) always remains stored inthe potential well beneath electrode G₂. This residual change levelplaces the operating point of the circuit at a desired point in thelinear region of the input transfer characteristic of the CCD.Superimposed over this residual charge level Q_(F) is an additionalcharge which may comprise a bias plus signal charge Q.sub.(B+S). Thisadditional charge subsequently is "skimmed" from the potential wellbeneath electrode G₂ and transmitted down the CCD register. The CCDchannel is relatively wide in the region of electrodes G₁, G₂ and G₃ andtapers down in width by an amount such that the maximum bias plus signalcharge Q.sub.(B+S) will fill the first potential well in the narrowestchannel region. In the example illustrated, the channel tapers fromwidth 2W to width W.

The operation above is depicted in the substrate potential profiles ofFIG. 4 when considered in connection with the operating waveforms ofFIG. 3. At time t₂, the voltage V_(S) applied to diffusion S causes thisdiffusion to operate as a source of charge carriers (electrons) andthese flow into the potential well 90 beneath electrode G₂. At time t₃,the voltage V_(S) is at a more positive level sufficiently so to causethe diffusion S to operate as a drain, and excess charge spills from thepotential well 90 back into the diffusion S. There remains in potentialwell 90 a residual charge level Q_(F) and a bias plus signal chargeQ.sub.(B+S). This bias plus signal charge includes a direct voltagecomponent whose value is dependent on the voltage V₁ applied to gateelectrode G₁. That is, this bias component is dependent on the level ofpotential barrier 92 in the absence of input signal. In the case of asymmetrical input signal V_(IN), the voltage V₁ will establish apotential barrier 92 such that the bias component of the chargeQ.sub.(B+S) will be at the center of the linear region of the inputcharacteristic. This may correspond, for example, to 1/2 the capacity ofthe potential well beneath electrode 94 in the main portion of the CCDchannel, that is, the narrowed down portion of the CCD channel as shownin FIG. 2. For an asymmetrical input signal, the votage V₁ can be madeto cause an operating point close to either end of the linear region ofthe input characteristic of the CCD, depending upon the direction ofasymmetry of the input signal. In one limiting case, V₁ may be at alevel such that Q_(B) is zero. In another it may be at a level such thatthe input potential well is full in the absence of a signal V_(IN).

At time t₄, when the voltage V₃ applied to the gate electrode G₃ is atits most positive value and when φ₁ is also at its most positive value,the charge Q.sub.(B+S) has transferred from well 90 to the potentialwell 96 now present beneath the first phase 1 (φ₁) electrode 98. Inother words, this charge Q.sub.(B+S) has been skimmed from the potentialwell 90, leaving behind the residual charge level Q_(F). The chargeQ.sub.(B+S) subsequently is propagated down the CCD in conventionalfashion.

In the operation of the system of the copending application identifiedabove, the voltage V₂ applied to gate electrode G₂ is held at a fixedlevel so that the residual charge Q_(F) also remains at a fixed level.The amount of charge propagated from potential well 90 (FIG. 4) topotential well 96, is a function of the difference in substratepotentials ΔV_(X) between substrate potentials at 92 and 99. These, inturn, are a function of the difference in potential V_(G1) -V₃ appliedto gate electrodes G₁ and G₃, respectively, where V_(G1) includes boththe DC and AC components applied to gate electrode G₁.

The present invention resides, in part, in the discovery that the gainof the input circuit to the CCD is a function of the voltage V₂ appliedto gate electrode G₂, that is, it is a function of the residual chargelevel Q_(F). The present inventor has found that for a given ΔV_(X), ifV₂ is made more positive, that is, if the size of the residual chargepacket Q_(F) is increased, the gain of the input circuit is increasedand vice-versa. This is illustrated in FIG. 4 by the last threesubstrate potential profiles. At time t₄, the voltage V₂ is at a levelsuch that a residual charge level Q_(F) remains in potential well 90 fora given difference in potential ΔV_(X) between surface potentials 92 and99. The transferred charge is Q.sub.(B+S) which subsequently ispropagated down the CCD. If V₂ is increased while the difference betweensurface potentials 92 and 99 remains the same, the amount of transferredcharge Q.sub.(B+S) ' increases. This is illustrated by the potentialprofiles at time t₃ ' and t₄ ' . In the former, which illustrates thespill portion of the cycle corresponding to t₃, V₂ has been made morepositive so that the residual charge component Q_(F) ' has beenincreased, that is, Q_(F) ' >Q_(F). At time t₄ ' corresponding to timet₄, the difference ΔV_(X) between substrate potentials 92 and 99 isequal to V_(Y) ; however, the amount of charge transferred Q.sub.(B+S) 'is greater than Q.sub.(B +S).

The reason for the above is not completely understood. However, thefollowing model may provide a basis for an explanation. It is believedthat as the voltage V₂ applied to the gate electrode G₂ is increased,the depth of the potential minimum of the conduction band increases andthe potential valley in the conduction band moves toward the surface 17of the N-type silicon layer as illustrated in the energy band diagram ofFIG. 5. The solid line illustrates the substrate potentials for a lowervalue of V₂ and the dashed line the shift which occurs when the voltageV₂ is increased in a sense to increase the residual charge level Q_(F).Note the shift in the potential minimum from 37 to 37a, 37a being closerto surface 17. This change in the position of the potential minimum isbelieved to be manifested as an effective increase in the capacitance Cof the CCD channel, and as the charge signal amplitude Q_(SIG) is afunction of this capacitance C, this increase Q_(SIG). The equationrelating these quantities is:

    Q.sub.SIG =Δ(V.sub.c -V.sub.G1)C

The family of curves of FIG. 6 illustrates the operation of the presentgain control circuit. Each curve was obtained by applying a linear rampV_(G1) to a gate electrode corresponding to G₁ while maintaining fixedthe voltage V₃ applied to a gate electrode corresponding to G₃. Eachcurve is for a different voltage level V₂ applied to an electrodecorresponding to G₂. The ordinate of the curves is output current. Itwas measured by sensing the current produced in the output circuit (adrain diffusion, not shown) of the CCD in response to the appliedvoltages. Note that at any particular value of voltage V_(G1), such asV_(Z), the input gain (slope) obtained is higher at higher values of V₂than at lower values of V₂ (except, of course, where the curves convergeat the zero output current crossing of the V_(G1) axis).

FIG. 7 illustrates an important use of the gain control circuit of thepresent application. This figure shows schematically, a comb filterwhich may be employed for commercial television. Details of this filterare given in copending application Ser. No. 781,303 for "ElectronicSignal Processing Apparatus" filed March 25, 1977 by Dalton H. Pritchardand assigned to the same assignee as the present application. In brief,it includes a 1H (1 horizontal line period) plus N CCD stage delay line20 in one branch, an inverter 22 and a N-stage CCD delay line 24 in asecond branch and a N-stage CCD delay line 26 in a third branch. In thisparticular example, N is assumed to be 2. Each 2-stage delay line has aninput circuit such as shown in FIG. 1. The video signal is capacitivelycoupled to gate electrode G₁ of lines 20 and 26 and the inverted videosignal is capacitively coupled to gate electrode G₁ of line 24. One gaincontrol voltage (V₂) is applied to gate G₂ of line 24 and another gaincontrol voltage (call it V₂ ' ) is applied to gate G₂ of line 26. Thelong delay line 20 also has an input circuit such as shown in FIG. 1;however the voltage V₂ supplied to its gate electrode need not be madecontrollable but can be left at a fixed level. The output signal of thelong delay line 20 is combined with that of the short (two-stage) delayline 26 to produce the luminance signal, and the output signal of thelong delay line 20 is combined with the output signal of the short(two-stage) delay line 24 to produce the chrominance signal. It isnecessary to adjust the relative gains of the short delay lines 24 and26 to obtain rejection notches of sufficient depth at the colorsubcarrier frequency 3.58 MHz (megahertz). The gain control circuit ofthe present application employed in each short delay line 24 and 26provides sufficient range to make this adjustment.

The present gain control is a significant improvement over a previousapproach known to the present inventor for controlling the respectivegains of the chrominance and luminance channels which requiredconsiderable on-chip transistor circuitry to balance the signals inthese channels. With the present circuit it has been found possible toachieve gain variation of about ±20%, for a voltage range of 6-14 voltsapplied to electrode G₂. The means for producing a voltage in this rangemay simply be a potentiometer such as illustrated at 30 in FIG. 1 or maybe a feedback circuit for automatically controlling the gain ofelectrode G₂. This gain variation is more than adequate for the balancecontrol just described for the comb filter of FIG. 7.

FIG. 8 illustrates a comb filter such as shown in FIG. 7 but withautomatic control of the gains of the short delay lines 24 and 26 bynegative feedback circuits. The long and short delay lines have the samestructure as described in connection with FIG. 7. The circuit includes,in addition, four band pass filters 30, 32, 34 and 36 and twodifferential amplifiers 38 and 40. The band pass filters are all tunedto the same particular frequency at or close to the center frequency3.58 MHz of the color subcarrier components of the signals being passedthrough these lines.

In operation, the output signal of short delay line 24 is suppliedthrough filter 32 to the inverting terminal of differential amplifier 38and the output of the long delay line 20 is supplied through band passfilter 30 to the non-inverting terminal of the differential amplifier38. In complementary fashion, the output of short delay line 26 issupplied through band pass filter 34 to the non-inverting terminal ofdifferential amplifier 40 and the output of the long delay line 20 isapplied through filter 36 to the inverting terminal of differentialamplifier 40. The differential amplifiers compare the signals theyreceive and adjust the gain of the short delay lines to control theoutput signal amplitude of these delay lines at the particular frequencyto which the band pass filters are tuned which as already mentioned, isat or close to the color subcarrier frequency of 3.58 MHz. The controlis in a sense to make the gain of the short delay lines equal to that ofthe long delay lines at this frequency. The result of operating in thisway is to automatically control the depth of the rejection notchesproduced by the comb filter to their minimum levels.

While the present invention has been illustrated as embodied in atwo-phase CCD, it is to be understood that it is equally applicable toCCD's operated by any practical number of phases. Further, while twolayer electrodes are shown, the invention is applicable also to singlelayer, triple layer and other well-known CCD structures. With respect totwo-phase structures, means other than the ion implants illustrated maybe employed for providing asymmetrical potential wells. Further, whilein the illustrated system the substrate is of P-type and the surfacelayer of N-type, the reverse may be the case with corresponding changein operating voltage polarity. Finally, it is to be understood that thepresent invention is also applicable to other (than "fill and spill" )forms of buried channel CCD's which employ a residual charge whichcontinually is present in an input potential well.

What is claimed is:
 1. In a buried channel charge-coupled device (CCD)of the type having a substrate of one conductivity type, a surface layerof different conductivity type, a source of charge carriers in thesubstrate, a charge storage region in the substrate whose potential iscontrolled by an overlying electrode, receptive of a charge from saidsource of charge carriers, and means for transferring from said storageregion to a transfer site in said substrate an amount Q_(S) of chargesignal which is dependent on the amplitude V_(IN) of an input signal andfor leaving behind in said storage region a residual charge at a givenlevel Q_(F) independent of the input signal amplitude; a method forsetting the transfer function ΔQ_(S) /ΔV_(IN) of said CCD atsubstantially a preselected value, said method comprising the stepsof:(a) varying the level of the voltage applied to said electrode withina range of levels to thereby adjust the level Q_(F) of said residualcharge and hence determine the value of said transfer function inaccordance with said electrode voltage level, said range of levelsincluding that particular electrode voltage level at which said transferfunction has said preselected value, and (b) terminating the variationof said electrode voltage level in response to said transfer functionreaching substantially said preselected value.
 2. The method defined inclaim 1, wherein step a) comprises;manually varying the level of thevoltage applied to said electrode within said range of levels.
 3. Themethod as defined in claim 2, wherein step a) comprises:automaticallyvarying the voltage applied to said electrode within said range oflevels in accordance with a negative feedback signal.
 4. In a buriedchannel charge-coupled device (CCD) of the type having a substrate ofone conductivity type, a surface layer of different conductivity type, asource of charge carriers in the substrate, a charge storage region inthe substrate whose potential is controlled by an overlying electrode,receptive of a charge from said source of charge carriers, means fortransferring from said storage region to a transfer site in saidsubstrate an amount Q_(S) of charge signal which is dependent on theamplitude V_(IN) of an input signal and for leaving behind in saidstorage region a residual charge at a given level independent of theinput signal amplitude, an output circuit for producing an outputsignal, and means for shifting charge from said transfer site to saidoutput circuit, the improvement comprisingmeans for controlling thetransfer function ΔQ_(S) /ΔV_(IN) of said CCD comprising means forproducing a second signal, and a feedback circuit responsive to saidoutput signal and to said second signal for supplying a voltage to saidelectrode for controlling the level of said residual charge.
 5. Incombination:a buried channel first charge-coupled device (CCD) of thetype having a substrate of one conductivity type, a surface layer ofdifferent conductivity type, a source of charge carriers in thesubstrate, a charge storage region in the substrate whose potential iscontrolled by an overlying electrode, receptive of a charge from saidsource of charge carriers, means for transferring from said storageregion to a transfer site in said substrate an amount Q_(S) of chargesignal which is dependent on the amplitude V_(IN) of an input signal andfor leaving behind in said storage region a residual charge at a givenlevel independent of the input signal amplitude, an output circuitreceptive of charge for producing an output signal, and electrode meanscoupled to said substrate and responsive to applied voltages forpropagating charge from said transfer site to said output circuit; aburied channel second CCD, having a substrate of one conductivity type,a surface layer of different conductivity type, input circuit meansresponsive to said input signal V_(IN) for producing an amount Q_(S) ofcharge signal in said substrate which is dependent on the amplitudeV_(IN) of said input signal, an output circuit receptive of charge forproducing an output signal, and electrode means coupled to saidsubstrate of said second CCD and responsive to applied voltages forpropagating charge from said transfer site of said second CCD to saidoutput circuit of said second CCD; and a feedback circuit coupled to theoutput circuit of each CCD, said feedback circuit including a comparatorfor comparing the output signal level in a particular frequency band atthe output of one CCD with the output signal level in the same frequencyband at the output of the other CCD, and a feedback connection from theoutput of said comparator to said electrode of said first CCD, forapplying a voltage to said electrode of a sense to make the signalssupplied to said comparator by said CCD's equal in value.